Lattice Synthesis Timing Report
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Lattice Synthesis Timing Report, Version
Sat Sep 23 20:46:48 2017
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved.
Report Information
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Design: JLX12832G_lcd
Constraint file:
Report level: verbose report, limited to 3 items per constraint
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================================================================================
Constraint: create_clock -period 1000.000000 -name clk0 [get_nets clk_in_c]
1025 items scored, 0 timing errors detected.
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Passed: The following path meets requirements by 987.138ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1P3IX CK \lcd_driver_u/delay_cnt_i0_i2 (from clk_in_c +)
Destination: FD1P3AX D \lcd_driver_u/main_state_i2 (to clk_in_c +)
Delay: 12.702ns (34.3% logic, 65.7% route), 10 logic levels.
Constraint Details:
12.702ns data_path \lcd_driver_u/delay_cnt_i0_i2 to \lcd_driver_u/main_state_i2 meets
1000.000ns delay constraint less
0.160ns L_S requirement (totaling 999.840ns) by 987.138ns
Path Details: \lcd_driver_u/delay_cnt_i0_i2 to \lcd_driver_u/main_state_i2
Name Fanout Delay (ns) Pins Resource(Cell.Net)
L_CO --- 0.444 CK to Q \lcd_driver_u/delay_cnt_i0_i2 (from clk_in_c)
Route 2 e 1.198 \lcd_driver_u/delay_cnt[2]
LUT4 --- 0.493 D to Z \lcd_driver_u/i14_4_lut
Route 1 e 0.941 \lcd_driver_u/n36
LUT4 --- 0.493 B to Z \lcd_driver_u/i18_4_lut
Route 1 e 0.941 \lcd_driver_u/n40
LUT4 --- 0.493 B to Z \lcd_driver_u/i20_4_lut
Route 1 e 0.941 \lcd_driver_u/n42_adj_522
LUT4 --- 0.493 B to Z \lcd_driver_u/i21_4_lut
Route 1 e 0.941 \lcd_driver_u/n9703
LUT4 --- 0.493 A to Z \lcd_driver_u/i1_4_lut_rep_94
Route 6 e 1.457 \lcd_driver_u/n10549
LUT4 --- 0.493 A to Z \lcd_driver_u/i4180_2_lut
Route 1 e 0.941 \lcd_driver_u/n6742
LUT4 --- 0.493 C to Z \lcd_driver_u/i1219_4_lut
Route 1 e 0.020 \lcd_driver_u/n14_adj_469
MUXL5 --- 0.233 ALUT to Z \lcd_driver_u/i16
Route 1 e 0.020 \lcd_driver_u/n7_adj_468
MUXL5 --- 0.233 D1 to Z \lcd_driver_u/main_state_3__I_0_193_Mux_2_i15
Route 1 e 0.941 \lcd_driver_u/main_state_3__N_73[2]
--------
12.702 (34.3% logic, 65.7% route), 10 logic levels.
Passed: The following path meets requirements by 987.138ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1P3IX CK \lcd_driver_u/delay_cnt_i0_i2 (from clk_in_c +)
Destination: FD1P3AX D \lcd_driver_u/main_state_i2 (to clk_in_c +)
Delay: 12.702ns (34.3% logic, 65.7% route), 10 logic levels.
Constraint Details:
12.702ns data_path \lcd_driver_u/delay_cnt_i0_i2 to \lcd_driver_u/main_state_i2 meets
1000.000ns delay constraint less
0.160ns L_S requirement (totaling 999.840ns) by 987.138ns
Path Details: \lcd_driver_u/delay_cnt_i0_i2 to \lcd_driver_u/main_state_i2
Name Fanout Delay (ns) Pins Resource(Cell.Net)
L_CO --- 0.444 CK to Q \lcd_driver_u/delay_cnt_i0_i2 (from clk_in_c)
Route 2 e 1.198 \lcd_driver_u/delay_cnt[2]
LUT4 --- 0.493 D to Z \lcd_driver_u/i14_4_lut
Route 1 e 0.941 \lcd_driver_u/n36
LUT4 --- 0.493 B to Z \lcd_driver_u/i18_4_lut
Route 1 e 0.941 \lcd_driver_u/n40
LUT4 --- 0.493 B to Z \lcd_driver_u/i20_4_lut
Route 1 e 0.941 \lcd_driver_u/n42_adj_522
LUT4 --- 0.493 B to Z \lcd_driver_u/i21_4_lut
Route 1 e 0.941 \lcd_driver_u/n9703
LUT4 --- 0.493 A to Z \lcd_driver_u/i1_4_lut_rep_94
Route 6 e 1.457 \lcd_driver_u/n10549
LUT4 --- 0.493 D to Z \lcd_driver_u/main_state_3__I_0_193_Mux_2_i8_4_lut
Route 1 e 0.941 \lcd_driver_u/n8_adj_520
LUT4 --- 0.493 A to Z \lcd_driver_u/i1219_4_lut
Route 1 e 0.020 \lcd_driver_u/n14_adj_469
MUXL5 --- 0.233 ALUT to Z \lcd_driver_u/i16
Route 1 e 0.020 \lcd_driver_u/n7_adj_468
MUXL5 --- 0.233 D1 to Z \lcd_driver_u/main_state_3__I_0_193_Mux_2_i15
Route 1 e 0.941 \lcd_driver_u/main_state_3__N_73[2]
--------
12.702 (34.3% logic, 65.7% route), 10 logic levels.
Passed: The following path meets requirements by 987.138ns
Logical Details: Cell type Pin type Cell name (clock net +/-)
Source: FD1P3IX CK \lcd_driver_u/delay_cnt_i0_i0 (from clk_in_c +)
Destination: FD1P3AX D \lcd_driver_u/main_state_i2 (to clk_in_c +)
Delay: 12.702ns (34.3% logic, 65.7% route), 10 logic levels.
Constraint Details:
12.702ns data_path \lcd_driver_u/delay_cnt_i0_i0 to \lcd_driver_u/main_state_i2 meets
1000.000ns delay constraint less
0.160ns L_S requirement (totaling 999.840ns) by 987.138ns
Path Details: \lcd_driver_u/delay_cnt_i0_i0 to \lcd_driver_u/main_state_i2
Name Fanout Delay (ns) Pins Resource(Cell.Net)
L_CO --- 0.444 CK to Q \lcd_driver_u/delay_cnt_i0_i0 (from clk_in_c)
Route 2 e 1.198 \lcd_driver_u/delay_cnt[0]
LUT4 --- 0.493 A to Z \lcd_driver_u/i4_2_lut
Route 1 e 0.941 \lcd_driver_u/n26_adj_524
LUT4 --- 0.493 C to Z \lcd_driver_u/i18_4_lut
Route 1 e 0.941 \lcd_driver_u/n40
LUT4 --- 0.493 B to Z \lcd_driver_u/i20_4_lut
Route 1 e 0.941 \lcd_driver_u/n42_adj_522
LUT4 --- 0.493 B to Z \lcd_driver_u/i21_4_lut
Route 1 e 0.941 \lcd_driver_u/n9703
LUT4 --- 0.493 A to Z \lcd_driver_u/i1_4_lut_rep_94
Route 6 e 1.457 \lcd_driver_u/n10549
LUT4 --- 0.493 D to Z \lcd_driver_u/main_state_3__I_0_193_Mux_2_i8_4_lut
Route 1 e 0.941 \lcd_driver_u/n8_adj_520
LUT4 --- 0.493 A to Z \lcd_driver_u/i1219_4_lut
Route 1 e 0.020 \lcd_driver_u/n14_adj_469
MUXL5 --- 0.233 ALUT to Z \lcd_driver_u/i16
Route 1 e 0.020 \lcd_driver_u/n7_adj_468
MUXL5 --- 0.233 D1 to Z \lcd_driver_u/main_state_3__I_0_193_Mux_2_i15
Route 1 e 0.941 \lcd_driver_u/main_state_3__N_73[2]
--------
12.702 (34.3% logic, 65.7% route), 10 logic levels.
Report: 12.862 ns is the maximum delay for this constraint.
Timing Report Summary
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Constraint | Constraint| Actual|Levels
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| | |
create_clock -period 1000.000000 -name | | |
clk0 [get_nets clk_in_c] | 1000.000 ns| 12.862 ns| 10
| | |
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All constraints were met.
Timing summary:
---------------
Timing errors: 0 Score: 0
Constraints cover 4255 paths, 515 nets, and 1515 connections (98.6% coverage)
Peak memory: 75325440 bytes, TRCE: 1449984 bytes, DLYMAN: 163840 bytes
CPU_TIME_REPORT: 0 secs